1. Field of the Invention
The present invention generally relates to a method and apparatus for bypassing memory arrays and in particular a method and apparatus for bypassing memory arrays in a very large scale integration (VLSI) circuit without an additional logic element.
2. Description of the Related Art
Memory arrays occupy a large portion of conventional very large scale integration (VLSI) circuits. Besides the basic functionality of read and write operations, additional (supporting) functions are needed, especially for an in-system test of the memory itself or of the logic attached to it. One of these features is conventionally referred to as a write-around or bypass circuit. It is used to display data from a separate port at the output of the memory, without affecting the array content.
FIG. 1 illustrates a conventional logic path 100. Referring to FIG. 1, data is launched by scannable latch 110, fed through logic 120 and received at the end by another scannable latch 130. System tests can easily be performed using the scan chain of conventional path 100.
When arrays get involved in a logic cone (e.g., multiple arrays or logic elements feeding into the same receiving flip-flop), performing the logic test becomes more difficult. This difficulty increases even more so in the case the array does not contain a scannable latch at the output but is directly connected to some downstream logic. In this configuration, it becomes more difficult to apply appropriate test-vectors to the logic cone. For this case, the “bypass” or “write-around” feature is required. The bypass feature is used to display data from a separate port at the output of the memory, without affecting the array content. A well-known and widely used method for realizing this function is a multiplexor circuit, which is connected to the memory output.
FIG. 2 illustrates a conventional bypass circuit 200 having multiplexor 240. Referring to FIG. 2, array 210 and scannable latch 230 would require the bypass or write-around circuit or feature. The bypass is used to display data from a separate port at the output of the memory without affecting the array content. One conventional method includes adding multiplexor 240 to array 210 which is connected to the output of memory 260. But this conventional solution has some drawbacks such as the requirement of an additional logic element to be placed in the timing critical output path of memory 260 or that a timing behavior of the bypassed data is different to the read data.
Adding a multiplexor to the VLSI circuit has the disadvantages in that an additional logic element has to be placed in the timing critical output path of the memory. The increased delay caused by the multiplexor limits the achievable maximum operating frequency. Timing behavior of the bypassed data is different than that of the read data. This timing difference makes time sensitive testing of the down-stream logic almost impossible.